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BU9829GUL-W (16Kbit)
Datasheet
● Functional description
○ Status Register
The device has status register.
Status register consists of 8bits and is shown following parameters.
2 bits (BP0 and BP1) are set by “Write Status Register” commands, which are non-volatile.
Specification of endurance and data retention are as well as memory array. WEN bit is set by “Write Enable” and “Write
Disable” commands. After power become on, the device is disable mode. R / B bit is a read-only and status bit.
The device is clocked out value of the status register by “Read Status Register” command input.
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
BP1
Bit2
BP0
Bit1
WEN
Bit0
R / B
Bit
BP0/BP1
WEN
Definition
Block write protection for memory array
(EEPROM)
Write enable/disable status bit
WEN=0 : write disable
WEN=1 : write enable
BP1
0
0
1
1
BP0
0
1
0
1
Block Write Protection
NONE
600h-7FFh
400h-7FFh
000h-7FFh
READY/BUSY status bit
R / B
R / B =0 : READY
R / B =1 : BUSY
● Instruction code
Instruction
Operation
Op.Code
Address
WREN
WRDI
READ
WRITE
RDSR
WRSR
VSET_READ
VSET_WRITE
Write enable
Write disable
Read data from memory array
Write data to memory array
Read status register
Write status register
Read VSET data
Write VSET data
0000
0000
0000
0000
0000
0000
0000
0000
0110
0100
0011
0010
0101
0001
0011
0010
-
-
A10 to A0
A10 to A0
-
-
800h
800h
● Timing chart
1. WRITE ENABLE
CSB
2. WRITE DISABLE
CSB
SCK
SI
0
0
0
1
0
2
0
3
0
4
1
5
1
6
0
7
SCK
SI
0
0
0
1
0
2
0
3
0
4
1
5
0
6
0
7
SO
Hi-Z
Figure 31. WRITE ENABLE CYCLE TIMING
SO
Hi-Z
Figure 32. WRITE DISABLE CYCLE TIMING
○ The device has both of the enable and disable mode. After “Write Enable” is executed, the device becomes in the enable
mode. After “Write Disable” is executed, the device becomes in the disable mode. After CSB goes low, each of Op.code
is recognized at the rising edge of 7th clock. Each of instructions is effective inputting seven or more SCK clocks. This
“Write Enable” instruction must be proceeded before the any write commands. The device ignores inputting the any write
commands in the disable mode. Once the any write commands is executed in the enable mode, the device becomes the
disable mode. After the power become on, the device is in the disable mode.
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
13/23
TSZ02201-0R2R0G100400-1-2
28.AUG.2012 Rev.001
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